Integrated semiconductor memories have a memory cell array with a multiplicity of memory cells for storing digital information and also a logic area for driving the memory cell array and for operating the semiconductor memory. Storage is effected in storage capacitors, which are driven via a selection transistor situated at the crossover point between a word line, which electrically opens or closes the transistor, and a bit line. Further transistors are arranged in the logic area, and are formed differently and dimensioned differently than selection transistors of memory cells. In particular, the tradeoff between the requirement to minimize space in the memory area on the wafer and the desired analog switching behavior of transistors of the logic area yield different selection criteria for the design of the transistors for the memory and logic areas, respectively.
One design of the selection transistor in the memory area is the surrounding gate transistor. Ridges made of substrate material formed by a vertical anisotropic etching are used as a basic structure for the formation of the transistor. In this case, the patterned, usually elongate, ridge is covered with a gate dielectric and surrounded from all sides, except for the top side, with a surrounding gate electrode formed by a spacer technique. A trench capacitor is arranged at one end of the ridge. A first, lower source/drain region is formed by outdiffusion from the inner capacitor electrode of the trench capacitor. On the top side of the ridge, a second, upper source/drain is formed by implantation. In this way a vertical selection transistor is produced in the ridge above the trench capacitor. Alternatively, the vertical selection transistors can be formed in the interior of a capacitor trench above the storage capacitor.
Furthermore, there are semiconductor memories with planar selection transistors in the memory cell array, which are arranged laterally with respect to the connected storage capacitors. These selection transistors do not have a ridge made of substrate material.
These designs of selection transistors are usually realized using field-effect transistors, in particular, MOSFETs (metal oxide semiconductor field effect transistors), in which, between two source/drain regions below a gate dielectric, an electrically conductive channel is formed by inversion of doped substrate material. The inversion channel has a channel length between the source and the drain, and a channel width, which corresponds to the optical resolution limit used.
In view of decreasing operating voltages and decreasing lateral dimensions of the memory cells with limited current density, the write and read speed cannot be increased sufficiently to the desired extent.
Moreover, leakage currents, which flow, for example, via the electrical connection between storage capacitor and selection transistor, cause a an early discharge of the storage capacitor which, in the case of dynamic semiconductor memories, shortens the refresh period and increases the current consumption of the memory.